Field of the Invention
The invention lies in the field of semiconductor technology. More specifically, the invention relates to a semiconductor chip, and to a method and a device for carrying out the method for fabricating the semiconductor chip using standard cells.
Standard cells are used to speed up the design of a semiconductor chip. Examples of the standard cells are gates, shift registers or other digital or analog modules which are formed from individual integrated components such as transistors, diodes or resistors and generally provide one or more standardized functions.
Standard cells are disclosed in U.S. Pat. No. 5,468,977 for example. These standard cells are arranged by way of a CAD system and subsequently wired by way of tracks. The tracks of a semiconductor chip designed in this way are insulated by an insulation layer perforated with contact holes for the connection of the tracks.
The standard cells are usually arranged along a plurality of mutually adjacent rows. The standard cells of a row are supplied with current by means of tracks that are arranged along the row. Depending on the number of voltages or currents required within the row, two or further tracks for power supply extend along the rows. The associated power supply tracks of each row are connected to one another and further elements or terminals of the semiconductor chip.
Moreover, provision is usually made of further tracks in particular for the transmission of analog or digital signals between the standard cells or to terminals of the semiconductor chip. The tracks are arranged in one or generally in a plurality of so-called metallization planes. These wiring planes can also be utilized for the arrangement of optical tracks, in particular optical conductors, in addition to metallic connections.
In order to arrange the tracks optimally, a so-called router program is used, which connects the inputs and outputs of the standard cells among one another and to terminals of the semiconductor chip. Afterward, the respective position or the course of the individual tracks is disentangled in order to enable the densest possible arrangement of the standard cells or of the tracks and the shortest possible signal delay. It goes without saying that, in addition to this known arrangement of standard cells and the wiring thereof, further arrangement specifications are conceivable, for example a vertical or function-related arrangement, for example for isolating a digital and an analog region of an ASIC or the like.
On account of the size and the geometry of the standard cell and the prescribed arrangement thereof within a plurality of rows, the space for the arrangement of the tracks is severely limited if an unnecessarily high number of metallization planes is to be prevented.